Optimizing Page Replacement for Multiple-Level Memory Hierarchy

Improvement in memory speeds has not kept pace with increasing processor speed. Consequently, the gap between processor and memory speed is growing. In order to meet the computational needs of the next decade, the design projects of PetaFlop computer introduce many levels of memory hierarchy with huge amount of speed differences between levels. Having memory hierarchy can reduce the penalty of cache misses. In this paper, mechanisms to control the data movement among the multiplelevel memory hierarchy are proposed to achieve an optimal number of cache misses. Two memory models are studied. The rst model consists of a uni-processor with one physical k-level memory hierarchy. We design an optimal algorithm data replacement under this platform. For the second model, multi-processor multi-level memory hierarchy, where, some levels may be physically shared by multiple processors. We design two data replacement approaches for this memory model. Our experimental results show the e ciency of our approaches by comparing with other standard schemes MIN and LRU. This work was partially supported by NSF MIP 95-01006 and NSF ACS 96-12028.